Siemens and TSMC are extending their semiconductor design collaboration through an AI-powered agent capable of identifying and fixing design rule violations across both digital and custom chip designs. Combining Siemens’ Calibre, Aprisa and Solido software, the integrated workflow is intended to reduce the manual work involved in checking whether a chip layout complies with the manufacturing rules required for a particular process before the completed design reaches tapeout.
Beyond layout verification, the shared initiative encompasses AI-assisted chip implementation alongside TSMC’s advanced manufacturing processes. The technical scope also reaches across 3D chip packaging architectures and silicon photonics.
AI handles more design rule checking
The automated workflow forms part of Siemens’ Fuse EDA AI System and Fuse EDA AI Agent, which are engineered to carry out longer, multi-step electronic design automation tasks. Siemens notes that the system can coordinate actions across several design tools, assess intermediate results and verify its work as a task progresses. To handle these longer-running workloads, the architecture incorporates NVIDIA AI technologies to improve token efficiency, reasoning and execution. In design rule checking, Calibre, Aprisa AI and Solido Fuse work in close coordination to identify, analyse and resolve violations, building on Calibre Check Assist to provide contextual guidance and design rule details when engineers investigate problems.
Siemens and TSMC are applying similar agent-based capabilities to custom chip design and physical implementation. Within this domain, Aprisa supports automated placement and routing, determining how components are arranged on a chip and how their connections are laid out.
“AI presents a significant opportunity to drive productivity and efficiency across increasingly complex semiconductor design workflows,” said Aveek Sarkar, director of the ecosystem and alliance management division at TSMC. “Our collaboration with OIP partners like Siemens focuses on delivering intelligent, trusted automation that empowers engineers to navigate rising design complexity while achieving stringent performance and energy-efficiency targets. By integrating AI into critical stages of the design process, we enable mutual customers to leverage TSMC’s industry-leading processes and advanced packaging technologies to accelerate the expansion of AI innovation.”
This joint deployment concentrates AI automation on defined engineering tasks where the software can check results during execution. In practice, this targeted approach addresses repetitive design-rule debugging and implementation work that would otherwise require far more manual intervention.
Work extends across 3D chip design
Siemens and TSMC are also expanding support for TSMC 3DFabric technologies, which are used to combine multiple dies and packaging technologies within more complex semiconductor designs. Calibre 3DStack Advanced now supports processing across multiple machines for inter-chiplet antenna verification, including designs using TSMC-SoIC wafer-level 3D stacking technology. Concurrently, certification work is under way for TSMC’s CoWoS-L packaging technology.
Their joint efforts cover thermal analysis, chip-package co-design and routing between separate dies. Calibre 3DThermal has been certified for static and transient thermal analysis of TSMC 3DFabric technologies and the TSMC A16 process, while enablement has been completed for a system-on-wafer thermal reference flow. In addition, Siemens and TSMC are progressing support for 3Dblox, TSMC’s framework for 3D chip design, including chip-package co-design workflows. Within this environment, Aprisa is being developed to automatically determine die-to-die routing configurations based on simulation results and signal-integrity requirements.
Silicon photonics forms another dimension of the collaboration through TSMC-COUPE, or Compact Universal Photonic Engine. Siemens tools have already been enabled for design, implementation and verification work using the technology, while further thermal validation remains in progress.
Siemens tools gain further TSMC certifications
Siemens has secured certifications for several verification tools on TSMC’s A14 process. These include Calibre nmDRC for checking design rules, Calibre nmLVS for comparing a physical chip layout with its circuit design, Calibre xACT for extracting electrical characteristics and Calibre PERC for electrical reliability checks. The Solido Simulation Suite is likewise certified for SPICE accuracy across TSMC N3C, A16 and A14 technologies, covering analogue, radio-frequency and memory verification.
For power integrity, Siemens’ mPower software is certified for transistor-level voltage-drop and electromigration analysis on TSMC N2P for digital and analogue designs, alongside N3C for analogue designs. Both companies are continuing work on N2 and N3 reference flows, while certification of Aprisa and mPower analogue software for A14 remains under way.
Broadening their technical ecosystem, Siemens has opened its Xcelerator Academy training programme to TSMC Design Center Alliance partners alongside mutual customers. This educational offering includes a digital implementation tutorial based on TSMC’s 5 nm process technology.
