AMD has announced a significant achievement in its partnership with TSMC, revealing that its upcoming AMD EPYC processor, codenamed “Venice,” is the first high-performance computing (HPC) product in the industry to be taped out and successfully brought up using TSMC’s advanced 2nm (N2) process technology. This milestone demonstrates the close collaboration between AMD and TSMC in developing next-generation design architectures alongside cutting-edge semiconductor process innovations.
The Venice processor represents a crucial step forward in AMD’s data centre CPU roadmap. It is currently on track to launch in 2026 and showcases AMD’s commitment to delivering high-performance and power-efficient solutions for enterprise computing. The news underlines the growing importance of process-node innovation in unlocking improvements across performance, energy efficiency, and chip yields.
Strengthening US manufacturing efforts
Alongside the Venice update, AMD also announced the successful bring-up and validation of its 5th Generation AMD EPYC CPUs at TSMC’s new fabrication plant in Arizona, Fab 21. This further highlights AMD’s ongoing investment in strengthening its U.S.-based manufacturing footprint, supporting the broader national initiative to enhance domestic semiconductor production.
“TSMC has been a key partner for many years and our deep collaboration with their R&D and manufacturing teams has enabled AMD to consistently deliver leadership products that push the limits of high-performance computing,” said Dr Lisa Su, chair and CEO of AMD. “Being a lead HPC customer for TSMC’s N2 process and for TSMC Arizona Fab 21 are great examples of how we are working closely together to drive innovation and deliver the advanced technologies that will power the future of computing.”
Partnership paves the way for next-generation computing
The partnership between AMD and TSMC continues to play a pivotal role in pushing semiconductor boundaries. TSMC’s N2 process is expected to bring substantial improvements in power efficiency and chip performance, benefits that will directly feed into AMD’s upcoming product generations. As silicon scaling becomes increasingly complex, such collaborative efforts are vital for sustaining progress across the tech industry.
Dr C.C. Wei, Chairman and CEO of TSMC, said, “We are proud to have AMD be a lead HPC customer for our advanced 2nm (N2) process technology and TSMC Arizona fab. By working together, we are driving significant technology scaling resulting in better performance, power efficiency and yields for high-performance silicon. We look forward to continuing to work closely with AMD to enable the next era of computing.”
As the industry moves towards more advanced nodes, AMD’s early involvement with the 2nm process and the operational readiness of TSMC’s Arizona facility reflect a strong roadmap for upcoming innovation in the data centre and enterprise computing space.
